1. Field of Invention
The present invention relates in general to a multiprocessor computer system and, in particular, to a method and apparatus for high speed, low overhead system bus arbitration between two processing devices, wherein each of the processing devices may comprise a microprocessor or a lesser device, such as a SCSI interface, math co-processor, or the like.
2. Background Art
Multiprocessor computers have long been known in the art. These computers have taken on numerous forms, such as processor/coprocessor, symmetric microprocessors, asymmetric microprocessors and microprocessor/DMA controllers. Wide spread use of Symmetric and asymmetric multiprocessing has been rather prohibitive due to the associated costs incurred as a result of the special requirements of such a system, including the requirement for custom designed processors for a multiprocessing environment, in turn, requiring custom applications for these systems. The converse of multiprocessor systems are, of course, uniprocessor computers.
The most popular and widely distributed uniprocessor systems utilize in their designs the INTEL 486 family of microprocessors (486SX, 486DX, 486DX2 and OverDrive processors), produced by the INTEL CORPORATION of Santa Clara, Calif. The cost of these processors is relatively inexpensive particularly when compared with specialty multiprocessor computer processors. Furthermore, because of the proliferation of INTEL based computers, software availability is very good. These elements have combined to make the INTEL 486 a `defacto` standard in the computer industry.
As a result of the popularity of the INTEL 486 family, the 486 bus definition, i.e. the defined signals and their timing, have become an industry standard with more and more chip set and peripheral manufacturers designing their products to work within this definition. Some more pertinent signals available in the bus definition include:
BREQ--The internal cycle pending signal indicates that the microprocessor has internally generated a bus request. BREQ is generated whether or not the microprocessor is driving the bus. PA1 RDY/--The non-burst ready input indicates that the current bus cycle is complete. RDY/ indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted data from the microprocessor in response to a write. RDY/ is ignored when the bus is idle and at the end of the first clock of the bus cycle. PA1 BRDY/--The burst ready input performs the same function during a burst cycle that RDY/ performs during a non-burst cycle. BRDY/ is ignored when the bus is idle and at the end of the first clock in a bus cycle. BRDY/ is sampled in the second and subsequent clocks of a burst cycle. PA1 BLAST/--The burst last signal indicates that the next time BRDY/ is returned the burst bus cycle is complete. PA1 LOCK/--The bus lock pin indicates that the current bus cycle is locked. LOCK/ goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when ready is returned. PA1 PLOCK/--The pseudo-lock pin indicates that the current bus transaction requires more than one bus cycle to complete. Examples of such operations are floating point long reads and writes (64 bits), segment table descriptor reads (64 bits), in addition to cache line fills (128 bits). The microprocessor will drive PLOCK/ active until the addresses for the last bus cycle of the transaction have been driven regardless of whether RDY/ or BRDY/ have been returned. PA1 ADS/--The address status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS/ is driven active in the same clock as the addresses are driven. PA1 EADS/--This signal indicates that a valid external address has been driven onto the microprocessor address pins. This address will be used to perform an internal cache invalidation cycle. PA1 M/IO, D/C, W/R--The bus definition signals are not driven during bus hold and follow the timing of the address bus.
Attempts have been made to interconnect 486 type microprocessors utilizing the 486 bus definition with some limited success. Many of the problems which are typically experienced are due to under utilization of bus cycles and/or existence of bus contention problems--typically resulting in less than optimum performance for the investment required.
It is thus an object of the present invention to provide a multiprocessor computer system utilizing commonly developed processing devices, such as the INTEL 486 family of microprocessors.
It is a further object to provide high speed, low overhead bus arbitration, while minimizing the need for additional, custom logic so as to minimize the cost of such a multiprocessor computer system.
It is yet a further object of the present invention to provide for a multiprocessing computer system having the ability to use commonly available software packages.
These and other objects will become apparent in light of the attached specification, drawings and claims.